2016 – 2017 Final Year Projects :: VLSI – Titles & Abstracts
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Titles 2016 – 2017 :: VLSI Projects
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ETPL VLSI – 001 |
MACS: A Highly Customizable Low-Latency Communication Architecture |
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ETPL VLSI – 002 |
Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication |
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ETPL VLSI – 003 |
DFSB-Based Thermal Management Scheme for 3-D NoC-Bus Architectures |
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ETPL VLSI – 004 |
LUT Optimization for Distributed Arithmetic-Based Block Least Mean Square Adaptive Filter |
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ETPL VLSI – 005 |
High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels |
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ETPL VLSI – 006 |
A New XOR-Free Approach for Implementation of Convolutional Encoder |
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ETPL VLSI – 007 |
A Low-Latency List Successive-Cancellation Decoding Implementation for Polar Codes |
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ETPL VLSI – 008 |
A Low-Power Broad-Bandwidth Noise Cancellation VLSI Circuit Design for In-Ear Headphones |
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ETPL VLSI – 009 |
Low-Power High-Density STT MRAMs on a 3-D Vertical Silicon Nanowire Platform |
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ETPL VLSI – 010 |
On the Total Power Capacity of Regular-LDPC Codes With Iterative Message-Passing Decoders |
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ETPL VLSI – 011 |
Assessing the Suitability of King Topologies for Interconnection Networks |
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ETPL VLSI – 012 |
A 6 b 5 GS/s 4 Interleaved 3 b/Cycle SAR ADC |
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ETPL VLSI – 013 |
Algorithm and Architecture of Configurable Joint Detection and Decoding for MIMO Wireless Communications with Convolutional |
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ETPL VLSI – 014 |
Power/Energy Minimization Techniques for Variability-Aware High-Performance 16-nm 6T-SRAM |
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ETPL VLSI – 015 |
A Single-Ended With Dynamic Feedback Control 8T Subthreshold SRAM Cell |
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ETPL VLSI – 016 |
A 3-D CPU-FPGA-DRAM Hybrid Architecture for Low-Power Computation |
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ETPL VLSI – 017 |
Streaming Elements for FPGA Signal and Image Processing Accelerators |
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ETPL VLSI – 018 |
High-Performance Pipelined Architecture of Elliptic Curve Scalar Multiplication Over GF( {2}^{m} ) |
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ETPL VLSI – 019 |
Read Bitline Sensing and Fast Local Write-Back Techniques in Hierarchical Bitline Architecture for Ultralow-Voltage SRAMs |
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ETPL VLSI – 020 |
A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications |
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ETPL VLSI – 021 |
A Novel Quantum-Dot Cellular Automata {X} -bit \times 32 -bit SRAM |
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ETPL VLSI – 022 |
Process Variation Delay and Congestion Aware Routing Algorithm for Asynchronous NoC Design |
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ETPL VLSI – 023 |
Designing Tunable Subthreshold Logic Circuits Using Adaptive Feedback Equalization |
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ETPL VLSI – 024 |
Flexible DSP Accelerator Architecture Exploiting Carry-Save Arithmetic |
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ETPL VLSI – 025 |
A Low-Power Robust Easily Cascaded PentaMTJ-Based Combinational and Sequential Circuits |
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ETPL VLSI – 026 |
Design of Modified Second-Order Frequency Transformations Based Variable Digital Filters with Large Cutoff Frequency Range and Improved Transition Band Characteristics |
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ETPL VLSI – 027 |
High-Speed, Low-Power, and Highly Reliable Frequency Multiplier for DLL-Based Clock Generator |
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ETPL VLSI – 028 |
Knowledge-Based Neural Network Model for FPGA Logical Architecture Development |
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ETPL VLSI – 029 |
Built-In Self-Test and Digital Calibration of Zero-IF RF Transceivers |
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ETPL VLSI – 030 |
A Systematic Design Methodology of Asynchronous SAR ADCs |
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ETPL VLSI – 031 |
Test Pattern Modification for Average IR-Drop Reduction |
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ETPL VLSI – 032 |
Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding |
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ETPL VLSI – 033 |
A Mismatch-Insensitive Skew Compensation Architecture for Clock Synchronization in 3-D ICs |
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ETPL VLSI – 034 |
High-Density and High-Reliability Nonvolatile Field-Programmable Gate Array With Stacked 1D2R RRAM Array |
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ETPL VLSI – 035 |
In-Field Test for Permanent Faults in FIFO Buffers of NoC Routers |
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ETPL VLSI – 036 |
A Comparator-Based Rail Clamp |
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ETPL VLSI – 037 |
A SUC-Based Full-Binary 6-bit 3.1-GS/s 17.7-mW Current-Steering DAC in 0.038 mm ^{2} |
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ETPL VLSI – 038 |
Glitch Energy Reduction and SFDR Enhancement Techniques for Low-Power Binary-Weighted Current-Steering DAC |
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ETPL VLSI – 039 |
Computing Seeds for LFSR-Based Test Generation From Nontest Cubes |
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ETPL VLSI – 040 |
Design for Testability of Sleep Convention Logic |
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ETPL VLSI – 041 |
An Efficient Single and Double-Adjacent Error Correcting Parallel Decoder for the (24,12) Extended Golay Code |
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ETPL VLSI – 042 |
Low-Power ECG-Based Processor for Predicting Ventricular Arrhythmia |
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ETPL VLSI – 043 |
Sequence-Aware Watermark Design for Soft IP Embedded Processors |
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ETPL VLSI – 044 |
A Configurable Parallel Hardware Architecture for Efficient Integral Histogram Image Computing |
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ETPL VLSI – 045 |
A Universal Hardware-Driven PVT and Layout-Aware Predictive Failure Analytics for SRAM |
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ETPL VLSI – 046 |
Error Resilient and Energy Efficient MRF Message-Passing-Based Stereo Matching |
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ETPL VLSI – 047 |
Unequal-Error-Protection Error Correction Codes for the Embedded Memories in Digital Signal Processors |
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ETPL VLSI – 048 |
Design of a High-Performance System for Secure Image Communication in the Internet of Things |
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ETPL VLSI – 049 |
Histogram-Based Ratio Mismatch Calibration for Bridge-DAC in 12-bit 120 MS/s SAR ADC |
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ETPL VLSI – 050 |
Energy and Area Efficient Three-Input XOR/XNORs With Systematic Cell Design Methodology |
