Research & Development Division
Call Us Free: 1-800-103-2221

2016-2017 Final Year Projects VLSI

2016 – 2017 Final Year Projects :: VLSI – Titles & Abstracts


Andriod_Application
[freebiesub download=”http://elysiumtechnologies.com/wp-content/uploads/2016/08/VLSI.pdf” title=”Get IEEE Abstract 2016 :: Services Computing”]




Get it Now! 5000+ IEEE Project Lists

Elysium feels proud in building strategic long-term relationships with the clients across worldwide. We believe that the best solutions evolve from the collaborative relationships with our clients. As a global consultant, we work closely with the clients to understand their unique business transformation goals, design best-in-class solutions and devise the most efficient plan for implementing their strategy across the organization.

Our ETPL is renowned for our reputed services in offering real time projects for the students of engineering and science stream. Our prime motto is to fulfill the needs of the students in every aspect of our work. We also extend our guidance services to the research scholars.

  • No.1 : Project Leader in India
  • 1,00,000 Sucessive Stories
  • 100% Satisfaction
  • 100% Privacy
  • 5000+ IEEE Project Titles
  • Qualified Staff Members
  • 24/7 Help Desk Support
Close this popup

Your Information will never be shared




Titles 2016 – 2017 :: VLSI Projects

ETPL VLSI – 001

MACS: A Highly Customizable Low-Latency Communication
Architecture

ETPL VLSI – 002

Low-Cost High-Performance VLSI Architecture for Montgomery
Modular Multiplication

ETPL VLSI – 003

DFSB-Based Thermal Management Scheme for 3-D NoC-Bus
Architectures

ETPL VLSI – 004

LUT Optimization for Distributed Arithmetic-Based Block Least Mean
Square Adaptive Filter

ETPL VLSI – 005

High-Speed and Energy-Efficient Carry Skip Adder Operating Under a
Wide Range of Supply Voltage Levels

ETPL VLSI – 006

A New XOR-Free Approach for Implementation of Convolutional
Encoder

ETPL VLSI – 007

A Low-Latency List Successive-Cancellation Decoding Implementation
for Polar Codes

ETPL VLSI – 008

A Low-Power Broad-Bandwidth Noise Cancellation VLSI Circuit
Design for In-Ear Headphones

ETPL VLSI – 009

Low-Power High-Density STT MRAMs on a 3-D Vertical Silicon
Nanowire Platform

ETPL VLSI – 010

On the Total Power Capacity of Regular-LDPC Codes With Iterative
Message-Passing Decoders

ETPL VLSI – 011

Assessing the Suitability of King Topologies for Interconnection
Networks

ETPL VLSI – 012

A 6 b 5 GS/s 4 Interleaved 3 b/Cycle SAR ADC

ETPL VLSI – 013

Algorithm and Architecture of Configurable Joint Detection and
Decoding for MIMO Wireless Communications with Convolutional

ETPL VLSI – 014

Power/Energy Minimization Techniques for Variability-Aware High-Performance 16-nm 6T-SRAM

ETPL VLSI – 015

A Single-Ended With Dynamic Feedback Control 8T Subthreshold
SRAM Cell

ETPL VLSI – 016

A 3-D CPU-FPGA-DRAM Hybrid Architecture for Low-Power
Computation

ETPL VLSI – 017

Streaming Elements for FPGA Signal and Image Processing Accelerators

ETPL VLSI – 018

High-Performance Pipelined Architecture of Elliptic Curve Scalar
Multiplication Over GF( {2}^{m} )

ETPL VLSI – 019

Read Bitline Sensing and Fast Local Write-Back Techniques in
Hierarchical Bitline Architecture for Ultralow-Voltage SRAMs

ETPL VLSI – 020

A High-Performance FIR Filter Architecture for Fixed and
Reconfigurable Applications

ETPL VLSI – 021

A Novel Quantum-Dot Cellular Automata {X} -bit \times 32 -bit SRAM

ETPL VLSI – 022

Process Variation Delay and Congestion Aware Routing Algorithm for
Asynchronous NoC Design

ETPL VLSI – 023

Designing Tunable Subthreshold Logic Circuits Using Adaptive
Feedback Equalization

ETPL VLSI – 024

Flexible DSP Accelerator Architecture Exploiting Carry-Save Arithmetic

ETPL VLSI – 025

A Low-Power Robust Easily Cascaded PentaMTJ-Based Combinational
and Sequential Circuits

ETPL VLSI – 026

Design of Modified Second-Order Frequency Transformations Based Variable Digital Filters
with Large Cutoff Frequency Range and Improved Transition Band Characteristics

ETPL VLSI – 027

High-Speed, Low-Power, and Highly Reliable Frequency Multiplier for
DLL-Based Clock Generator

ETPL VLSI – 028

Knowledge-Based Neural Network Model for FPGA Logical
Architecture Development

ETPL VLSI – 029

Built-In Self-Test and Digital Calibration of Zero-IF RF Transceivers

ETPL VLSI – 030

A Systematic Design Methodology of Asynchronous SAR ADCs

ETPL VLSI – 031

Test Pattern Modification for Average IR-Drop Reduction

ETPL VLSI – 032

Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units
for Video Encoding

ETPL VLSI – 033

A Mismatch-Insensitive Skew Compensation Architecture for Clock
Synchronization in 3-D ICs

ETPL VLSI – 034

High-Density and High-Reliability Nonvolatile Field-Programmable
Gate Array With Stacked 1D2R RRAM Array

ETPL VLSI – 035

In-Field Test for Permanent Faults in FIFO Buffers of NoC Routers

ETPL VLSI – 036

A Comparator-Based Rail Clamp

ETPL VLSI – 037

A SUC-Based Full-Binary 6-bit 3.1-GS/s 17.7-mW Current-Steering
DAC in 0.038 mm ^{2}

ETPL VLSI – 038

Glitch Energy Reduction and SFDR Enhancement Techniques for Low-Power Binary-Weighted Current-Steering DAC

ETPL VLSI – 039

Computing Seeds for LFSR-Based Test Generation From Nontest Cubes

ETPL VLSI – 040

Design for Testability of Sleep Convention Logic

ETPL VLSI – 041

An Efficient Single and Double-Adjacent Error Correcting Parallel
Decoder for the (24,12) Extended Golay Code

ETPL VLSI – 042

Low-Power ECG-Based Processor for Predicting Ventricular Arrhythmia

ETPL VLSI – 043

Sequence-Aware Watermark Design for Soft IP Embedded Processors

ETPL VLSI – 044

A Configurable Parallel Hardware Architecture for Efficient Integral
Histogram Image Computing

ETPL VLSI – 045

A Universal Hardware-Driven PVT and Layout-Aware Predictive
Failure Analytics for SRAM

ETPL VLSI – 046

Error Resilient and Energy Efficient MRF Message-Passing-Based
Stereo Matching

ETPL VLSI – 047

Unequal-Error-Protection Error Correction Codes for the Embedded
Memories in Digital Signal Processors

ETPL VLSI – 048

Design of a High-Performance System for Secure Image Communication
in the Internet of Things

ETPL VLSI – 049

Histogram-Based Ratio Mismatch Calibration for Bridge-DAC in 12-bit
120 MS/s SAR ADC

ETPL VLSI – 050

Energy and Area Efficient Three-Input XOR/XNORs With Systematic
Cell Design Methodology

august, 2018

Sort Options

No Events

Latest Posts

Login Form

LiveZilla Live Chat Software

Get it Now! 5000+ IEEE Project Lists

Elysium feels proud in building strategic long-term relationships with the clients across worldwide. We believe that the best solutions evolve from the collaborative relationships with our clients. As a global consultant, we work closely with the clients to understand their unique business transformation goals, design best-in-class solutions and devise the most efficient plan for implementing their strategy across the organization.

Our ETPL is renowned for our reputed services in offering real time projects for the students of engineering and science stream. Our prime motto is to fulfill the needs of the students in every aspect of our work. We also extend our guidance services to the research scholars.

  • No.1 : Project Leader in India
  • 1,00,000 Sucessive Stories
  • 100% Satisfaction
  • 100% Privacy
  • 5000+ IEEE Project Titles
  • Qualified Staff Members
  • 24/7 Help Desk Support
Close this popup

Your Information will never be shared

Your Name
Your Mobile Number
Your E-Mail ID
*All information provided will be kept confidential.
*Terms & Conditions Apply
Your Name
Your Mobile Number
Your E-Mail ID
*All information provided will be kept confidential.
*Terms & Conditions Apply
Your Name
Your Mobile Number
Your E-Mail ID
*All information provided will be kept confidential.
*Terms & Conditions Apply