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2017 2018 Final Year Projects VLSI

2017 – 2018 Final Year Projects :: VLSI – Titles & Abstracts


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Titles 2017 – 2018 :: VLSI Projects

ETPL VLSI – 001

A Variation-Tolerant Near-Threshold Processor With Instruction-Level
Error Correction

ETPL VLSI – 002

Digital 2-/3-Phase Switched-Capacitor Converter with Ripple Reduction
and Efficiency Improvement

ETPL VLSI – 003

Sudden Power-Outage Resilient In-Processor Check pointing for
Energy-Harvesting Nonvolatile Processors

ETPL VLSI – 004

A CMOS Ultrawideband Pulse Generator for 3–5 GHz Applications

ETPL VLSI – 005

Analytical Models of High-Speed RLC Interconnect Delay for Complex
and Real Poles

ETPL VLSI – 006

An 80.4% Peak Power Efficiency Adaptive Supply Class H Power
Amplifier for Audio Applications

ETPL VLSI – 007

Two-Extra-Column Trellis Min–Max Decoder Architecture for
Nonbinary LDPC Codes

ETPL VLSI – 008

A 0.13- µm CMOS Dynamically Reconfigurable Charge Pump for
Electrostatic MEMS Actuation

ETPL VLSI – 009

Ultra-Low Power, Highly Reliable, and Nonvolatile Hybrid MTJ/CMOS
Based Full-Adder for Future VLSI Design

ETPL VLSI – 010

Low power-delay-product dynamic CMOS circuit design techniques

ETPL VLSI – 011

Energy-Efficient VLSI Realization of Binary64 Division with
Redundant Number Systems

ETPL VLSI – 012

A General Digit-Serial Architecture for Montgomery Modular
Multiplication

ETPL VLSI – 013

Conditional-Boosting Flip-Flop for Near-Threshold Voltage
Application

ETPL VLSI – 014

Delay Analysis for Current Mode Threshold Logic Gate Design

ETPL VLSI – 015

Efficient Multi-rate Encoder of QC-LDPC Codes Based on FPGA for
WIMAX Standard

ETPL VLSI – 016

Low-Complexity Transformed Encoder Architectures for Quasi-Cyclic
Nonbinary LDPC Codes Over Subfields

ETPL VLSI – 017

Practical Encoder and Decoder for Power Constrained QC LDPC-Lattice
Codes

ETPL VLSI – 018

Comparative study of 16-order FIR filter design using different
multiplication techniques

ETPL VLSI – 019

On the VLSI Energy Complexity of LDPC Decoder Circuits

ETPL VLSI – 020

A Statistical Design Approach Using Fixed and Variable Width
Transconductors for Positive-Feedback Gain-Enhancement OTAs

ETPL VLSI – 021

Design of a CMOS Chlorophyll Concentration Detector Based on
Organic Chlorophyll Battery for Measuring Vegetable Chlorophyll
Concentration

ETPL VLSI – 022

Novel Radiation-Hardened-by-Design (RHBD) 12T Memory Cell for
Aerospace Applications in Nanoscale CMOS Technology

ETPL VLSI – 023

A High-Efficiency 6.78-MHz Full Active Rectifier With Adaptive Time
Delay Control for Wireless Power Transmission

ETPL VLSI – 024

Design of Defect and Fault-Tolerant Nonvolatile Spintronic Flip-Flops

ETPL VLSI – 025

A 0.1–2-GHz Quadrature Correction Loop for Digital Multiphase Clock
Generation Circuits in 130-nm CMOS

ETPL VLSI – 026

A Multiphase Switched-Capacitor DC–DC Converter Ring With Fast
Transient Response and Small Ripple

ETPL VLSI – 027

A 5-Gb/s Digital Clock and Data Recovery Circuit With Reduced DCO
Supply Noise Sensitivity Utilizing Coupling Network

ETPL VLSI – 028

28-nm Latch-Type Sense Amplifier Modification for Coupling
Suppression

ETPL VLSI – 029

10T SRAM Using Half- VDD Precharge and Row-Wise Dynamically
Powered Read Port for Low Switching Power and Ultralow RBL
Leakage

ETPL VLSI – 030

Power-Gated 9T SRAM Cell for Low-Energy Operation

ETPL VLSI – 031

Area and Energy-Efficient Complementary Dual-Modular Redundancy
Dynamic Memory for Space Applications

ETPL VLSI – 032

Reliability Enhancement of Low-Power Sequential Circuits Using
Reconfigurable Pulsed Latches

ETPL VLSI – 033

Reliability-Tolerant Design for Ultra-Thin-Body GeOI 6T SRAM Cell
and Sense Amplifier

ETPL VLSI – 034

RS flip-flop implementation based on all spin logic devices

ETPL VLSI – 035

Area- and power-efficient iterative single/double-precision merged
floating-point multiplier on FPGA

ETPL VLSI – 036

Design of Efficient BCD Adders in Quantum-Dot Cellular Automata

ETPL VLSI – 037

Reconfigurable Constant Multiplication for FPGAs

ETPL VLSI – 038

Reliable Low-Latency Viterbi Algorithm Architectures Benchmarked on
ASIC and FPGA

ETPL VLSI – 039

A 250-Mb/s to 6-Gb/s Referenceless Clock and Data Recovery Circuit
With Clock Frequency Multiplier

ETPL VLSI – 040

V -band ×8 Frequency Multiplier With Optimized Structure and High
Spectral Purity Using 65-nm CMOS Process

ETPL VLSI – 041

Design of Power and Area Efficient Approximate Multipliers

ETPL VLSI – 042

Design and Analysis of Multiplier Using Approximate 15-4 Compressor

ETPL VLSI – 044

Optimized Memristor-Based Multipliers

ETPL VLSI – 044

16 × 1 Packaged MUX/DEMUX for Flexible-Grid Optical Networks

ETPL VLSI – 045

High-performance engineered gate transistor-based compact digital
circuits

ETPL VLSI – 046

A Fault Tolerance Technique for Combinational Circuits Based on
Selective-Transistor Redundancy

ETPL VLSI – 047

Design of Low-Power High-Performance 2–4 and 4–16 Mixed-Logic
Line Decoders

ETPL VLSI – 048

Analysis and Design of the Classical CMOS Schmitt Trigger in Sub
threshold Operation

ETPL VLSI – 049

Highly Tunable Triangular Wave UWB Baseband Pulse Generator With
Amplitude Stabilization in 40-nm CMOS

ETPL VLSI – 050

A Study of Injection Locking in Dual-Band CMOS Frequency Dividers

ETPL VLSI – 051

Design of On-Chip Readout Circuitry for Spin-Wave Devices

june, 2018

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