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IEEE 2013 Final Year Projects | VLSI

IEEE 2013  Final Year Projects :: VLSI – Titles & Abstracts


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IEEE Titles 2013 :: VLSI

ETPL – VLSI 001 Pragmatic Integration of an SRAM Row Cache in Heterogeneous 3-D DRAM Architecture Using TSV
ETPL – VLSI 002 A Low-Complexity Turbo Decoder Architecture for Energy-Efficient Wireless Sensor Networks
ETPL – VLSI 003 Pipelined Radix- 2k Feedforward FFT Architectures
ETPL – VLSI 004 Algorithm and Architecture Design of Bandwidth-Oriented Motion Estimation for Real-Time Mobile Video Applications
ETPL – VLSI 005 STBC-OFDM Downlink Baseband Receiver for Mobile WMAN
ETPL – VLSI 006 Glitch-Free NAND-Based Digitally Controlled Delay-Lines
ETPL – VLSI 007 A High-Efficiency, Wide Workload Range, Digital Off-Time Modulation (DOTM) DC-DC Converter With Asynchronous Power Saving Technique
ETPL – VLSI 008 Formal Verification of Architectural Power Intent
ETPL – VLSI 009 Statistical SRAM Read Access Yield Improvement Using Negative Capacitance Circuits
ETPL – VLSI 010 An Energy-Efficient L2 Cache Architecture Using Way Tag Information Under Write-Through Policy
ETPL – VLSI 011 An Analytical Latency Model for Networks-on-Chip
ETPL – VLSI 012 Built-In Generation of Functional Broadside Tests Using a Fixed Hardware Structure
ETPL – VLSI 013 Checkpointing for Virtual Platforms and SystemC-TLM
ETPL – VLSI 014 Design of a Practical Nanometer-Scale Redundant Via-Aware Standard Cell Library for Improved Redundant Via1 Insertion Rate
ETPL – VLSI 015 Scaling Energy Per Operation via an Asynchronous Pipeline
ETPL – VLSI 016 A High Speed Low Power CAM With a Parity Bit and Power-Gated ML Sensing
ETPL – VLSI 017 Error Detection in Majority Logic Decoding of Euclidean Geometry Low Density Parity Check (EG-LDPC) Codes
ETPL – VLSI 018 Techniques for Compensating Memory Errors in JPEG2000
ETPL – VLSI 019 Spatial Distribution Measurement of Dynamic Voltage Drop Caused by Pulse and Periodic Injection of Spot Noise
ETPL – VLSI 020 Low-Complexity Multiplier for  GF(2^{m}) Based on All-One Polynomials
ETPL – VLSI 021 Design and Implementation of an On-Chip Permutation Network for Multiprocessor System-On-Chip
ETPL – VLSI 022 An On-Chip Network Fabric Supporting Coarse-Grained Processor Array
ETPL – VLSI 023 A Very Linear Low-Pass Filter with Automatic Frequency Tuning
ETPL – VLSI 024 A High-Speed Low-Complexity Modified  {\rm Radix}-2^{5} FFT Processor for High Rate WPAN Applications
ETPL – VLSI 025 Application Space Exploration of a Heterogeneous Run-Time Configurable Digital Signal Processor
ETPL – VLSI 026 A Unified Graphics and Vision Processor With a 0.89  \mu W/fps Pose Estimation Engine for Augmented Reality
ETPL – VLSI 027 CORDIC Designs for Fixed Angle of Rotation
ETPL – VLSI 028 Application-Driven End-to-End Traffic Predictions for Low Power NoC Design
ETPL – VLSI 029 Thermal-Constrained Task Allocation for Interconnect Energy Reduction in 3-D Homogeneous MPSoCs
ETPL – VLSI 030 A Wide-Range PLL Using Self-Healing Prescaler/VCO in 65-nm CMOS
ETPL – VLSI 031 A Clock Control Strategy for Peak Power and RMS Current Reduction Using Path Clustering
ETPL – VLSI 032 A Fast-Locking All-Digital Deskew Buffer With Duty-Cycle Correction
ETPL – VLSI 033 A Built-In Repair Analyzer With Optimal Repair Rate for Word-Oriented Memories
ETPL – VLSI 034 System-Level Modeling and Analysis of Thermal Effects in Optical Networks-on-Chip
ETPL – VLSI 035 A Study of Tapered 3-D TSVs for Power and Thermal Integrity
ETPL – VLSI 036 Improved Trace Buffer Observation via Selective Data Capture Using 2-D Compaction for Post-Silicon Debug
ETPL – VLSI 037 AC-Plus Scan Methodology for Small Delay Testing and Characterization
ETPL – VLSI 038 A Variation Tolerant Current-Mode Signaling Scheme for On-Chip Interconnects
ETPL – VLSI 039 Modeling and Analysis of Power Distribution Networks in 3-D ICs
ETPL – VLSI 040 A Low-Cost, Systematic Methodology for Soft Error Robustness of Logic Circuits
ETPL – VLSI 041 Low Complexity Out-of-Order Issue Logic Using Static Circuits
ETPL – VLSI 042 Low Latency Systolic Montgomery Multiplier for Finite Field  GF(2^{m}) Based on Pentanomials
ETPL – VLSI 043 Power-Up Sequence Control for MTCMOS Designs
ETPL – VLSI 044 Architecture and Design Flow for a Highly Efficient Structured ASIC
ETPL – VLSI 045 Secure Dual-Core Cryptoprocessor for Pairings Over Barreto-Naehrig Curves on FPGA Platform,
ETPL – VLSI 046 In-Situ Method for TSV Delay Testing and Characterization Using Input Sensitivity Analysis
ETPL – VLSI 047 Low-Resolution DAC-Driven Linearity Testing of Higher Resolution ADCs Using Polynomial Fitting Measurements
ETPL – VLSI 048 Low-Cost Error Tolerance Scheme for 3-D CMOS Imagers
ETPL – VLSI 049 Computing Two-Pattern Test Cubes for Transition Path Delay Faults
ETPL – VLSI 050 Integrated Energy-Harvesting Photodiodes With Diffractive Storage Capacitance
ETPL – VLSI 051 Fast Fixed-Outline 3-D IC Floorplanning With TSV Co-Placement
ETPL – VLSI 052 Reactivation Noise Suppression With Sleep Signal Slew Rate Modulation in MTCMOS Circuits
ETPL – VLSI 053 Sub-mW  LC Dual-Input Injection-Locked Oscillator for Autonomous WBSNs
ETPL – VLSI 054 Constant Delay Logic Style
ETPL – VLSI 055 A Compact Clock Generator for Heterogeneous GALS MPSoCs in 65-nm CMOS Technology
ETPL – VLSI 056 A Colpitts CMOS Quadrature VCO Using Direct Connection of Substrates for Coupling
ETPL – VLSI 057 A Self-Calibrated DLL-Based Clock Generator for an Energy-Aware EISC Processor
ETPL – VLSI 058 Clamping Virtual Supply Voltage of Power-Gated Circuits for Active Leakage Reduction and Gate-Oxide Reliability
ETPL – VLSI 059 10-bit 30-MS/s SAR ADC Using a Switchback Switching Method
ETPL – VLSI 060 Spur-Reduction Frequency Synthesizer Exploiting Randomly Selected PFD
ETPL – VLSI 061 Gain-Enhanced Monolithic Charge Pump With Simultaneous Dynamic Gate and Substrate Control
ETPL – VLSI 062 Embedding Repeaters in Silicon IPs for Cross-IP Interconnections
ETPL – VLSI 063 RATS: Restoration-Aware Trace Signal Selection for Post-Silicon Validation
ETPL – VLSI 064 Test Patterns of Multiple SIC Vectors: Theory and Application in BIST Schemes
ETPL – VLSI 065 Effective and Efficient Approach for Power Reduction by Using Multi-Bit Flip-Flops
ETPL – VLSI 066 Reconfigurable Accelerator for the Word-Matching Stage of BLASTN
ETPL – VLSI 067 Architecturally Homogeneous Power-Performance Heterogeneous Multicore Systems
ETPL – VLSI 068 Active Filter-Based Hybrid On-Chip DC–DC Converter for Point-of-Load Voltage Regulation
ETPL – VLSI 069 CusNoC: Fast Full-Chip Custom NoC Generation
ETPL – VLSI 070 Cooperating Virtual Memory and Write Buffer Management for Flash-Based Storage Systems
ETPL – VLSI 071 MDC FFT/IFFT Processor With Variable Length for MIMO-OFDM Systems
ETPL – VLSI 072 Current-Reused 2.4-GHz Direct-Modulation Transmitter With On-Chip Automatic Tuning
ETPL – VLSI 073 Reconfigurable Adaptive Singular Value Decomposition Engine Design for High-Throughput MIMO-OFDM Systems
ETPL – VLSI 074 The LUT-SR Family of Uniform Random Number Generators for FPGA Architectures
ETPL – VLSI 075 Exploring the Use of Emerging Nonvolatile Memory Technologies in Future FPGAs,
ETPL – VLSI 076 Broadside and Skewed-Load Tests Under Primary Input Constraints
ETPL – VLSI 077 Supply Noise Suppression by Triple-Well Structure
ETPL – VLSI 078 Software-Based Self Test Methodology for On-Line Testing of L1 Caches in Multithreaded Multicore Architectures
ETPL – VLSI 079 Design of Ternary Logic Combinational Circuits Based on Quantum Dot Gate FETs
ETPL – VLSI 080 Parametric DFM Solution for Analog Circuits: Electrical-Driven Hotspot Detection, Analysis, and Correction Flow
ETPL – VLSI 081 Unified Capture Scheme for Small Delay Defect Detection and Aging Prediction
ETPL – VLSI 082 Novel MIMO Detection Algorithm for High-Order Constellations in the Complex Domain
ETPL – VLSI 083 High-Throughput 0.13- \mu{\rm m} CMOS Lattice Reduction Core Supporting 880 Mb/s Detection
ETPL – VLSI 084 Study of Through-Silicon-Via Impact on the 3-D Stacked IC Layout
ETPL – VLSI 085 Design of Hardware Function Evaluators Using Low-Overhead Nonuniform Segmentation With Address Remapping
ETPL – VLSI 086 Statistical Functional Yield Estimation and Enhancement of CNFET-Based VLSI Circuits
ETPL – VLSI 087 Theoretical Modeling of Elliptic Curve Scalar Multiplier on LUT-Based FPGAs for Area and Speed,
ETPL – VLSI 088 Architecture for Real-Time Nonparametric Probability Density Function Estimation
ETPL – VLSI 089 Symbolic Moment Computation for Statistical Analysis of Large Interconnect Networks,
ETPL – VLSI 090 C-Based Complex Event Processing on Reconfigurable Hardware
ETPL – VLSI 091 Task Allocation on Nonvolatile-Memory-Based Hybrid Main Memory
ETPL – VLSI 092 BilRC: An Execution Triggered Coarse Grained Reconfigurable Architecture
ETPL – VLSI 093 Block-Circulant RS-LDPC Code: Code Construction and Efficient Decoder Design
ETPL – VLSI 094 Fault Demotion Using Reconfigurable Slack (FaDReS)
ETPL – VLSI 095 MAEPER: Matching Access and Error Patterns With Error-Free Resource for Low Vcc L1 Cache

april, 2018

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Elysium feels proud in building strategic long-term relationships with the clients across worldwide. We believe that the best solutions evolve from the collaborative relationships with our clients. As a global consultant, we work closely with the clients to understand their unique business transformation goals, design best-in-class solutions and devise the most efficient plan for implementing their strategy across the organization.

Our ETPL is renowned for our reputed services in offering real time projects for the students of engineering and science stream. Our prime motto is to fulfill the needs of the students in every aspect of our work. We also extend our guidance services to the research scholars.

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Elysium feels proud in building strategic long-term relationships with the clients across worldwide. We believe that the best solutions evolve from the collaborative relationships with our clients. As a global consultant, we work closely with the clients to understand their unique business transformation goals, design best-in-class solutions and devise the most efficient plan for implementing their strategy across the organization.

Our ETPL is renowned for our reputed services in offering real time projects for the students of engineering and science stream. Our prime motto is to fulfill the needs of the students in every aspect of our work. We also extend our guidance services to the research scholars.

  • No.1 : Project Leader in India
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  • 5000+ IEEE Project Titles
  • Qualified Staff Members
  • 24/7 Help Desk Support
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