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IEEE 2014 Final Year Projects | VLSI

IEEE 2014 Final Year Projects :: VLSI – Titles & Abstracts


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IEEE Titles 2014 :: VLSI

essays on communism in america nuclear fission research paper usc thesis library ap central sample essays literature essay contest kids horses disadvantages of pollution essay bernard lewis thesis format of an argumentative essay writing ETPL VLSI-001

Efficient VLSI Architecture For Interpolation Decoding Of Hermitia Codes

ETPL VLSI-002

Designing Hardware-Efficient Fixed-Point FIR Filters In An Expanding Subexpression Space

ETPL VLSI-003

Synchronous Non-Volatile Logic Gate Design Based on Resistive Switching Memories

ETPL VLSI-004

An Optimized Modified Booth Recoder for Efficient Design of the Add- Multiply Operator

ETPL VLSI-005

Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal Feed-Through

ETPL VLSI-006

Area-Delay-Power Efficient Fixed-Point LMS Adaptive Filter With Low Adaptation-Delay

ETPL VLSI-007

Rate-0.96 LDPC Decoding VLSI for Soft-Decision Error Correction of NAND Flash Memory

ETPL VLSI-008

A Generalized Lattice Filter for Finite Wordlength Implementation With Reduced Number of Multipliers

ETPL VLSI-009

Area-Delay-Power Efficient Fixed-Point LMS Adaptive Filter With Low Adaptation-Delay

ETPL VLSI-010

Finite Alphabet Iterative Decoders for LDPC Codes: Optimization, Architecture and Analysis

ETPL VLSI-011

Precise VLSI Architecture for AI Based 1-D/ 2-D Daub-6 Wavelet Filter Banks With Low Adder-Count

ETPL VLSI-012

Design of Efficient Binary Comparators in Quantum-Dot Cellular Automata

ETPL VLSI-013

Improved matrix multiplier design for high-speed digital signal processing applications

ETPL VLSI-014

High-Speed Experimental Demonstration of Adiabatic Quantum-Flux-Parametron Gates Using Quantum-Flux-Latches

ETPL VLSI-015

Spin Orbit Torque Non-Volatile Flip-Flop for High Speed and Low Energy Applications

ETPL VLSI-016

Critical-Path Analysis and Low-Complexity Implementation of the LMS Adaptive Algorithm

ETPL VLSI-017

Exploiting the Incomplete Diffusion Feature: A Specialized Analytical Side-Channel Attack Against the AES and Its Application to Microcontroller Implementations

ETPL VLSI-018

Efficient Register Renaming and Recovery for High-Performance Processors

ETPL VLSI-019

Design and simulation of power efficient traffic light controller (PTLC)

ETPL VLSI-020

Energy Efficient Exact Matching for Flow Identification with Cuckoo Affinity Hashing

ETPL VLSI-021

Ultra Low Power Magnetic Flip-Flop Based on Checkpointing/Power Gating and Self-Enable Mechanisms

ETPL VLSI-022

A joint encryption and error correction method used in satellite communications

ETPL VLSI-023

Dynamic ternary cam for hardware search engine

ETPL VLSI-024

High-Throughput Low-Energy Self-Timed CAM Based on Reordered Overlapped Search Mechanism

ETPL VLSI-025

A Single-Bit and Double-Adjacent Error Correcting Parallel Decoder for Multiple-Bit Error Correcting BCH Codes

ETPL VLSI-026

Design and implementation of high speed and high accuracy fixed-width modified booth multiplier for DSP application

ETPL VLSI-027

A new design of low power high speed hybrid CMOS full adder

ETPL VLSI-028

Design for reliability for low power digital circuits

ETPL VLSI-029

High speed vedic multiplier designs-A review

ETPL VLSI-030

Design of an energy efficient, high speed, low power full subtractor using GDI technique

ETPL VLSI-031

Ultrafast All-Optical Flip-Flops, Simultaneous Comparator-Decoder and Reconfigurable Logic Unit With Silicon Microring Resonator Switches

ETPL VLSI-032

Implementation of high speed low power combinational and sequential circuits using reversible logic

ETPL VLSI-033

An all-digital delay-locked loop for high-speed memory interface applications

ETPL VLSI-034

Low Power Square and Cube Architectures Using Vedic Sutras

ETPL VLSI-035

Performance analysis of a high speed, energy efficient 4×4 dynamic RAM cell array using 32nm fully depleted SOI/SON and CNFET

ETPL VLSI-036

High-performance 64-bit binary comparator

ETPL VLSI-037

FPGA based partial reconfigurable fir filter design

ETPL VLSI-038

Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator

ETPL VLSI-039

A Blind Dynamic Fingerprinting Technique for Sequential Circuit Intellectual Property Protection

ETPL VLSI-040

Area-Delay-Power Efficient Fixed-Point LMS Adaptive Filter With Low Adaptation-Delay

ETPL VLSI-041

Reduced-Complexity Min-Sum Algorithm for Decoding LDPC Codes With Low Error-Floor

ETPL VLSI-042

Improved 8-Point Approximate DCT for Image and Video Compression Requiring Only 14 Additions

ETPL VLSI-043

Toward Multi-Gigabit Wireless: Design of High-Throughput MIMO Detectors With Hardware-Efficient Architecture

ETPL VLSI-044

Partial Access Mode: New Method for Reducing Power Consumption of Dynamic Random Access Memory

ETPL VLSI-045

Pulsed-Latch Utilization for Clock-Tree Power Optimization

ETPL VLSI-046

Scalable Montgomery Modular Multiplication Architecture with Low-Latency and Low-Memory Bandwidth Requirement

ETPL VLSI-047

Reconfigurable CORDIC-Based Low-Power DCT Architecture Based on Data Priority

ETPL VLSI-048

Achieving High-Performance On-Chip Networks With Shared-Buffer Routers

ETPL VLSI-049

Area-Delay Efficient Binary Adders in QCA

ETPL VLSI-050

Low-Complexity Reconfigurable Fast Filter Bank for Multi-Standard Wireless Receivers

ETPL VLSI-051

Input Vector Monitoring Concurrent BIST Architecture Using SRAM Cells

ETPL VLSI-052

Low-Complexity Low-Latency Architecture for Matching of Data Encoded With Hard Systematic Error-Correcting Codes

ETPL VLSI-053

Layout-Based Refined NPSF Model for DRAM Characterization and Testing

ETPL VLSI-054

Parasitics-Aware Design of Symmetric and Asymmetric Gate-Workfunction FinFET SRAMs

ETPL VLSI-055

Simplifying Clock Gating Logic by Matching Factored Forms

ETPL VLSI-056

Design Flow for Flip-Flop Grouping in Data-Driven Clock Gating

ETPL VLSI-057

An Efficient Partial-Sum Network Architecture for Semi-Parallel Polar Codes Decoder Implementation

ETPL VLSI-058

An Analog VLSI Implementation of the Inner Hair Cell and Auditory Nerve Using a Dual AGC Model

ETPL VLSI-059

Improved Accuracy Current-Mode Multiplier Circuits With Applications in Analog Signal Processing

ETPL VLSI-060

Low-Complexity Low-Latency Architecture for Matching of Data Encoded With Hard Systematic Error-Correcting Codes

ETPL VLSI-061

AWARE (Asymmetric Write Architecture With REdundant Blocks): A High Write Speed STT-MRAM Cache Architecture

ETPL VLSI-062

Design of a Low-Voltage Low-Dropout Regulator

ETPL VLSI-063

An Analytical Delay Model for Mechanical Stress Induced Systematic Variability Analysis in Nanoscale Circuit Design

ETPL VLSI-064

Energy Efficient Programmable MIMO Decoder Accelerator Chip in 65-nm CMOS

ETPL VLSI-065

Iterative Linear Interpolation Based on Fuzzy Gradient Model for Low-Cost VLSI Implementation

ETPL VLSI-066

Simplifying Clock Gating Logic by Matching Factored Forms

ETPL VLSI-067

Use of SSTA Tools for Evaluating BTI Impact on Combinational Circuits

ETPL VLSI-068

Precise VLSI Architecture for AI Based 1-D/ 2-D Daub-6 Wavelet Filter Banks With Low Adder-Count

ETPL VLSI-069

An Optimized Modified Booth Recoder for Efficient Design of the Add-Multiply Operator

ETPL VLSI-070

Synchronous Non-Volatile Logic Gate Design Based on Resistive Switching Memories

ETPL VLSI-071

High-Throughput Multistandard Transform Core Supporting MPEG/H.264/VC-1 Using Common Sharing Distributed Arithmetic

ETPL VLSI-072

High-Throughput Multistandard Transform Core Supporting MPEG/H.264/VC-1 Using Common Sharing Distributed Arithmetic

ETPL VLSI-073

Simultaneous Low-Pass Filtering and Total Variation Denoising

ETPL VLSI-074

Effects of Random Delay Errors in Continuous-Time Semi-Digital Transversal Filters

ETPL VLSI-075

Two Polynomial FIR Filter Structures With Variable Fractional Delay and Phase Shift

ETPL VLSI-076

Algorithms and Architectures of Energy-Efficient Error-Resilient MIMO Detectors for Memory-Dominated Wireless Communication Systems

ETPL VLSI-077

A Methodology for Optimized Design of Secure Differential Logic Gates for DPA Resistant Circuits

ETPL VLSI-078

Reliability-Oriented Placement and Routing Algorithm for SRAM-Based FPGAs

ETPL VLSI-079

Eliminating Synchronization Latency Using Sequenced Latching

ETPL VLSI-080

Partial Access Mode: New Method for Reducing Power Consumption of Dynamic Random Access Memory

ETPL VLSI-081

Pulsed-Latch Utilization for Clock-Tree Power Optimization

ETPL VLSI-082

Toward Multi-Gigabit Wireless: Design of High-Throughput MIMO Detectors With Hardware-Efficient Architecture

ETPL VLSI-083

Finite Alphabet Iterative Decoders for LDPC Codes: Optimization, Architecture and Analysis

ETPL VLSI-084

Constructing Sub-Arrays with ShortInterconnects from Degradable VLSI Arrays

ETPL VLSI-085

A Lattice Reduction-Aided MIMO Channel Equalizer in 90 nm CMOS Achieving 720 Mb/s

ETPL VLSI-086

Evaluation of Leakage Reduction Alternatives for Deep Submicron Dynamic Nonuniform Cache Architecture Caches

ETPL VLSI-087

Split-SAR ADCs: Improved Linearity With Power and Speed Optimization

ETPL VLSI-088

An Event-Based Neural Network Architecture With an Asynchronous Programmable Synaptic Memory

ETPL VLSI-089

Low-Power Digital Signal Processor Architecture for Wireless Sensor Nodes

ETPL VLSI-090

Partial Access Mode: New Method for Reducing Power Consumption of Dynamic Random Access Memory

ETPL VLSI-091

Optimization Scheme to Minimize Reference Resistance Distribution of Spin-Transfer-Torque MRAM

ETPL VLSI-092

Towards Low-Power High-Efficiency RF and Microwave Energy Harvesting

ETPL VLSI-093

Access Time and Power Dissipation of a Model 256-Bit Single Flux Quantum RAM

ETPL VLSI-094

All-Optical Ultrafast Switching in 2 × 2 Silicon Microring Resonators and its Application to Reconfigurable DEMUX/MUX and Reversible Logic Gates

ETPL VLSI-095

Using Lifetime-Aware Progressive Programming to Improve SLC NAND Flash Memory Write Endurance

ETPL VLSI-096

Design of a Low-Voltage Low-Dropout Regulator

ETPL VLSI-097

Test Compaction by Sharing of Transparent-Scan Sequences Among Logic Blocks

ETPL VLSI-098

Multifunction Residue Architectures for Cryptography

ETPL VLSI-099

Scalable Montgomery Modular Multiplication Architecture with Low-Latency and Low-Memory Bandwidth Requirement

ETPL VLSI-100

An Efficient Partial-Sum Network Architecture for Semi-Parallel Polar Codes Decoder Implementation

ETPL VLSI-101

Improved Matching-Pursuit Implementation for LTE Channel Estimation

ETPL VLSI-102

A Multicast Tree Router for Multichip Neuromorphic Systems

ETPL VLSI-103

VLSI implementation of high-throughput parallel H.264/AVC baseline intra-predictor

july, 2017

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