2015 – 2016 Final Year Projects ::VLSI – Titles & Abstracts
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2015 – 2016 Final Year Projects :: VLSI
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ETPL VLSI-001 |
An Efficient VLSI Architecture of a Reconfigurable Pulse-Shaping FIR Interpolation |
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ETPL VLSI-002 |
A High-Throughput VLSI Architecture for Hard and Soft SC-FDMA MIMO Detectors |
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ETPL VLSI-003 |
VLSI-Assisted Nonrigid Registration Using Modified Demons Algorithm |
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ETPL VLSI-004 |
A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications |
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ETPL VLSI-005 |
Partially Parallel Encoder Architecture for Long Polar Codes |
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ETPL VLSI-006 |
Detailed Routing Algorithms for Advanced Technology Nodes |
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ETPL VLSI-007 |
Variations in Nanometer CMOS Flip-Flops: Part II—Energy Variability and Impact of Other Sources of Variations |
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ETPL VLSI-008 |
Design of a CMOS System-on-Chip for Passive, Near-Field Ultrasonic Energy Harvesting and Back-Telemetry |
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ETPL VLSI-009 |
An Inter/Intra-Chip Optical Network for Manycore Processors |
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ETPL VLSI-010 |
Aurora: A Cross-Layer Solution for Thermally Resilient Photonic Network-on- Chip |
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ETPL VLSI-011 |
High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels |
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ETPL VLSI-012 |
Design of Efficient Binary Comparators in Quantum-Dot Cellular Automata |
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ETPL VLSI-013 |
Improved matrix multiplier design for high-speed digital signal processing applications |
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ETPL VLSI-014 |
High-Speed Experimental Demonstration of Adiabatic Quantum-Flux- Parametron Gates Using Quantum-Flux-Latches |
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ETPL VLSI-015 |
Spin Orbit Torque Non-Volatile Flip-Flop for High Speed and Low Energy Applications |
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ETPL VLSI-016 |
Critical-Path Analysis and Low-Complexity Implementation of the LMS Adaptive Algorithm |
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ETPL VLSI-017 |
Exploiting the Incomplete Diffusion Feature: A Specialized Analytical Side-Channel Attack Against the AES and Its Application to Microcontroller Implementations |
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ETPL VLSI-018 |
Efficient Register Renaming and Recovery for High-Performance Processors |
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ETPL VLSI-019 |
Design and simulation of power efficient traffic light controller (PTLC) |
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ETPL VLSI-020 |
Reliable Low-Power Multiplier Design Using Fixed-Width Replica Redundancy Block |
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ETPL VLSI-021 |
Unified VLSI architecture for photo core transform used in JPEG XR |
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ETPL VLSI-022 |
An Efficient Constant Multiplier Architecture Based on Vertical-Horizontal Binary Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter |
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ETPL VLSI-023 |
Impact of TFET Unidirectionality and Ambipolarity on the Performance of 6T SRAM Cells |
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ETPL VLSI-024 |
High-Throughput LDPC-Decoder Architecture Using Efficient Comparison Techniques & Dynamic Multi-Frame Processing Schedule |
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ETPL VLSI-025 |
Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic |
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ETPL VLSI-026 |
A Synergetic Use of Bloom Filters for Error Detection and Correction |
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ETPL VLSI-027 |
Level-Converting Retention Flip-Flop for Reducing Standby Power in ZigBee SoCs |
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ETPL VLSI-028 |
Economizing TSV Resources in 3-D Network-on-Chip Design |
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ETPL VLSI-029 |
Architecture-Aware Analytical Yield Model for Read Access in Static Random Access Memory |
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ETPL VLSI-030 |
Design of Efficient Content Addressable Memories in High-Performance FinFET Technology |
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ETPL VLSI-031 |
Algorithm and Architecture for a Low-Power Content-Addressable Memory Based on Sparse Clustered Networks |
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ETPL VLSI-032 |
A Low-Latency and Low-Power Hybrid Scheme for On-Chip Networks |
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ETPL VLSI-033 |
Trigger-Wave Asynchronous Cellular Logic Array for Fast Binary Image Processing |
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ETPL VLSI-034 |
An Implantable Versatile Electrode-Driving ASIC for Chronic Epidural Stimulation in Rats |
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ETPL VLSI-035 |
Low-Power VLSI Architectures for DCT/DWT: Precision vs Approximation for HD Video, Biomedical, and Smart Antenna Applications |
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ETPL VLSI-036 |
11.25-ms-Group-Delay and Low-Complexity Algorithm Design of 18-Band Quasi-ANSI S1.11 1/3 Octave Digital Filterbank for Hearing Aids |
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ETPL VLSI-037 |
A Fully-Integrated Low-Dropout Regulator With Full-Spectrum Power Supply Rejection |
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ETPL VLSI-038 |
Read Performance: The Newest Barrier in Scaled STT-RAM |
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ETPL VLSI-039 |
A 16-mW 8-Bit 1-GS/s Digital-Subranging ADC in 55-nm CMOS |
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ETPL VLSI-040 |
Frequency-Tuning Negative-Conductance Boosted Structure and Applications for Low-Voltage Low-Power Wide-Tuning-Range VCO |
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ETPL VLSI-041 |
Z-TCAM: An SRAM-based Architecture for TCAM |
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ETPL VLSI-042 |
Nonsmooth Optimization Method for VLSI Global Placement |
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ETPL VLSI-043 |
Energy Consumption of VLSI Decoders |
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ETPL VLSI-044 |
Skewed-Load Test Cubes Based on Functional Broadside Tests for a Low- Power Test Set |
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ETPL VLSI-045 |
All Digital Energy Sensing for Minimum Energy Tracking |
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ETPL VLSI-046 |
Fat-Tree-Based Optical Interconnection Networks Under Crosstalk Noise Constraint |
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ETPL VLSI-047 |
Architecture-Aware Analytical Yield Model for Read Access in Static Random Access Memory |
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ETPL VLSI-048 |
A 0.325 V, 600-kHz, 40-nm 72-kb 9T Subthreshold SRAM with Aligned Boosted Write Wordline and Negative Write Bitline Write-Assist |
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ETPL VLSI-049 |
A CMOS PWM Transceiver Using Self-Referenced Edge Detection |
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ETPL VLSI-050 |
Low Overhead Software Wear Leveling for Hybrid PCM + DRAM Main Memory on Embedded Systems |
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ETPL VLSI-051 |
Recursive Approach to the Design of a Parallel Self-Timed Adder |
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ETPL VLSI-052 |
On the Nonvolatile Performance of Flip-Flop/SRAM Cells With a Single MTJ |
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ETPL VLSI-053 |
Design of Efficient Content Addressable Memories in High-Performance FinFET Technology |
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ETPL VLSI-054 |
Range Unlimited Delay-Interleaving and -Recycling Clock Skew Compensation and Duty-Cycle Correction Circuit |
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ETPL VLSI-055 |
A Fast Transient Response Flying-Capacitor Buck-Boost Converter Utilizing Pseudocurrent Dynamic Acceleration Techniques |
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ETPL VLSI-056 |
A Low-Cost Low-Power All-Digital Spread-Spectrum Clock Generator |
